1. Field of the Invention
The present invention relates to Random Access Memories (RAMs). Specifically, it relates to high speed, high density DRAMs.
2. Discussion of the Related Art
Today's electronic systems, specially computer systems, require high speed, high density memories. The increase in the capacity of the memories is directly proportional to their physical size. However, the trend is toward smaller systems that require smaller components, such as memory. Memory designers and manufacturers are constantly thriving to design high speed and high density memories without increasing the overall physical size of the memories.
The existing memory types include read only memory, flash memory, random access memory, etc. For the purposes of the present invention, we will discuss the architecture of a Random Access Memory ("RAM").
A conventional RAM includes memory array that is arranged in rows and columns of memory cells. The memory array further includes a word line associated with each row and a pair of complementary bit lines associated with each column of memory cells. By asserting the appropriate word line and bit lines, the information stored in a memory cell can be read or information can be written in to the memory cell.
In a typical read operation the information stored in a memory cell is transferred to the associated bit line. The information is then sensed by a sense amplifier and is placed on the I/O line. Typically, a pair of complementary I/O lines are used in the random access memories. In addition, there is one sense amplifier for every pair of bit lines.
As mentioned above, an increase in the number of memory cells results in an increase in the physical size of the die, thus increasing the physical size of the memory chip. In addition, as the number of memory cells in a memory chip increases, so does the physical length of the I/O lines.
To place the information, such as data, on an I/O lines, the associated sense amplifier must drive the I/O line. The speed by which each I/O line is driven is determined by its impedance. The impedance of an I/O line is determined by its inherent resistance, its inherent capacitance, and the capacitance of the pass transistors that are connected between the sense amplifier and the I/O line. The inherent resistance and capacitance of the I/O line depends on the material used to implement the I/O line and its physical shape. The longer is the length of an I/O line, the higher are the inherent capacitance and resistance of the I/O line.
On the other hand, an increase in the number of memory cells results in an increase in the number of sense amplifiers that are connectable to the I/O line via pass transistors. Thus, the total capacitance that is connected to the I/O lines increases.
Consequently, an increase in the number of memory cells associated with an I/O line results in an increases in the length of the I/O line and the number of pass transistors connected to the I/O line. Hence, the impedance of the I/O line as seen by the associated sense amplifiers increases. This means that the speed by which the sense amplifiers can drive the I/O lines decreases, which reduces the speed of the memory chip.
In view of the above, it is clear that high density and high speed memories require an architecture that allows for the increase in the capacity of the memory without a decrease in the performance speed.